1. You need to build a circuit to perform parallel data transfers from one set of registers to another. The interconnections between the registers must be held to a minimum. The best choice for the register FFs is the __________ type.

2. What is the output frequency of a three-stage binary counter with an input clock frequency of 80 kHz?

3. A NAND latch has outputs of Q = 1 and Q’ = 0 . What effect will applying a LOW to the CLEAR input have on the latch?

4. What is the output state of a MOD-64 counter after 92 input pulses if the starting state is 000000?

5. A 1.5 MHZ clock signal is applied to an eight flip-flop binary counter. What is the MOD number, maximum number of counts, maximum count, and output frequency of the circuit?

6. How many shift pulses would be required to serially shift the contents of one six-stage register to another?

7. Three flip-flops are wired together as a binary counter and the input clock frequency is 600 Hz. What is the output frequency of the highest order Q output?

8. Forcing the SET input LOW on a NAND gate latch generates outputs of:

9. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

10. Determine the output frequency for a binary counter that contains twelve flip-flops with an input clock frequency of 20.48 MHz.

Answers

1. The type is JK, flip-flop.

2. A three stage binary counter counts $2^3 = 8$ states. Hence the output frequency is $80/2^3 =80/8 =10 KHz$

3. A HIGH to the CLEAR input of a latch is forcing the output in 0. A LOW to the CLEAR input on a latch leaves the output unchanged. Hence $Q=1$, $Q’ =0$.

4. A mod 64 counter counts 64 states. Because the 0 state in included it numbers from 0 to 63 and the state 64 is zero. Hence the state 92 is equivalent to $92-64 = 32$. The output is 32.

5. The MOD number is $2^8 =256$. The maximum number of counts is 256 (=MOD number). The maximum count is 255 since the 0 state is included. Output frequency = $int(1.5*10^6/256) =int (5859.375) Hz =5860 Hz$ where $int$ is the integer part of.

6. Since one shift pulse shifts the contents of the register with one bit to the left or to the right, to shift with six bits one will need six pulses.

7. The output of the lower order Q will be $600/2$. The output of the middle order Q will be $600/2^2$. The output of the highest order Q will be $600/2^3 =600/8 =75 Hz$

8. On a NAND gate having SET and RESET as inputs, forcing SET on LOW will generate a HIGH output.

9. The clock pulse rise and fall times must be less than the propagation time of the signal through the flip-flop.

10. Output frequency is $F_{out} = 20.48*10^6/2^12 =2048*10^4/4096 =5000 Hz =5 KHz$